74HC138 : 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting DIP-16

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3-to-8 Line Decoder/Demultiplexer


The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The MM74HC138 has 3 binary select inputs (A, B, and C). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading of decoders. The decoder's outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equivalent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and ground.


  • Typical propagation delay: 20 ns
  • Low quiescent current: 80 mA maximum (74HC Series)
  • Low input current: 1 mA maximum
  • Fanout of 10 LS-TTL loads

Products specifications
Attribute nameAttribute value
CPU TypeGoogle